Semiconductor Consulting Services, Expert Witness, and Patent Litigation Support

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New Process Technology

• Qualcomm, Globalfoundries +30%  in Sales in 2012
• FinFET Layout Design and Variability
• IEDM 2012 Preview: 20nm and Smaller
• IEDM 2012 Program
• Intel's 14nm Process and Manufacturing Roadmap
• Apple's A6X Processor 32nm Process Advantages
• Latest Microsoft Surface TearDown
• Toshiba Next NAND- 3D with 15 Layers
•  Next iPhone A7 Made by TSMC not Samsung
• Semiconductor Foundries:Strong Q2, but Slowdown..
• Lenovo Prove: Outsourcing is Not the Only Way (Updated)
• DRAM Market Plateau/ Flash NAND Growing
• Apple Cutting Out Samsung Chips?
• iPhone A6 Teardown Update
•  Japan Fading in Semiconductor Fabrication?

• NAND:Prices, Market Shares (Micron Up, Toshiba Down..)

• iPhone A6 Performance Improvement
• iPhone Teardown Updated
• iPhone 5 Cost $199 BOM
• Samsung, a Top IC Foundry in 2012

• Smartphone Patent Wars Solutions
• Semiconductor Ranking: Foundries Soar, Japanese Crash
• Samsung, Hynix, Micron DRAM Monopoly?
• TSMC: Single-Customer (Apple? Qualcomm?) Fabs Make Sense
• ARM, TSMC Following Intel Lead
• Smartphone Dark Horse: Huawei
• Qualcom, Intel, Samsung, TSMC and foundary Business
• Flash NOR Memory Revival
• Top Patent Recipients (33% Semiconductor Companies)
• 450-mm-fabs-ramp-in-2017
• NAND Flash +DRAM Improves Memory Sys
• Intel, ASML: Higher Performance/ Lower Cost Edge
• Nexus 7 Tablet Teardown: +4% Mem. Cost Add $50 Profit
• Lenovo Prove: Outsourcing is Not the Only Way
• Samsung, Qualcomm: New Foundry Business Model
• Status of China's Fabless Model
• Hynix Developing PCM, MRAM, and ReRAM Flash
• Apple's iPad, iCloud Drive Semiconductor Industry
• 2012 Q1 Ranking: Toshiba Outperforms NAND Market
• Intel: "Fabless model collapsing". Is it correct?
• Qualcomm and Nvidia Chip Shortage
• TSMC 28nm Capacity Large Shortage
• New Foundry Ranking (By IC Insights)
• Intel/ Micron 20-nm 64G MLC NAND Flash Memory Reverse Engineered
• Foundry Rankings (Including Samsungs' iPad, iPhone Breakdown)
• While FinFET Charging Ahead, Other 20nm challenges
• Qualcomm, Intel Fastest Growing Semiconductor Companies
• Nvidia: TSMC 20nm Essentially Worthless
• Moore's Law Slowwwing Since 28nm Process Node
• New iPad-Teardown: Why Apple's A5X uses 45nm
• Are Japan's Fabs stuck above 28nm Process Technology?
• iPad Teardown - Flash NAND Memory is a Major Profit Source

• Moore's Law End? (Next semiconductors generation cost $10 billion)
• When will the Flash be 2x DRAM Memory Market?
• Is Resistive RAM (RRAM) The Future Flash Memory?
• 2011 IEDM Full Technical Program, Previews
• Intel Developer Forum - Tri-Gate for Socs, 14nm process, TSV, 2.5D, and 3D stacking
• Semiconductor Plant Rebooted Three Months Faster After The Japanese Earthquake
• Intel 22nm 3D Tri-Gate FinFETs Transistors: Faster, Cooler, Smaller
• Semiconductor News: Japan Earthquake Impact Electronic Supply Chain
• ISSCC 2011 Highlights- 20-nm Process Challenges, Samsung 512-pins DRAM, Intel SandyBridge, AMD Bulldozer
• 2010 International Technology Roadmap for Semiconductors (ITRS) Updates
• All about 3D integration - Design, Process, Devices, Integration, Manufacturing Articles and Forums
• 2010 IEDM Update
• 2010 IEDM Full Technical Program, Previews
• Robotics for Electronics Manufacturing (e.g. Clean Rooom)
• Robotics for Electronics Mfg Book (Sample Chapter Semiconductor Robotic Manufacturing)
• Semiconductor IC Ranking 2009 (Samsung, Hynix growing, SanDisk surprise)
• Integrating High-k Metal Gate: First or Last
• TSMC Use a Gate-Last Deposition Process for the High-k/Metal Gate Stack of its 28 nmTransistors
• IEDM 2009 - Will IBM Shift to Gate-Last; Intel 32 nm PMOS; Silicon CMOS for 22 nm; Logic Processes
• How much of a lead does Intel have at 32nm and for High-K Metal Gate (HKMG) Technologies?
• Lithography Manufacturing Beyond 22nm
• IEDM 2009 - NEC, Toshiba, and IMEC Devices
• Semiconductor Industry Trends in Light of 2008 Economic Upheaval
• IEDM 2009 Preview
• Semiconductor IC Ranking Q3 2009 (fast growth at Samsung, Toshiba, Hynix, Micron)

• Intel's 32nm Silicon Technology - Microprocessor and System-on-Chip (SOC)
• Globalfoundries (GF) More Advanced Than TSMC
• Semiconductor Inventory and its Impact on Electronic Supply Chains- iSupply
• Semiconductor IC Ranking Q2 2009(Climbing TSMC, Hynix, MediaTek Droping AMD, Freescale, Fujitsu)
• Samsung- 5 nm is Not a Limit to Silicon Scaling
• VLSI 2009 - Updates
• Toshiba announces high-k/Ge gate stack technology for 16nm
• Tungsten Plug Issues and 32 nm Process
• Scalling to 22 nm Process
• 15 Technology Challenges for 22-nm Node
• 450-nm Fabs Status
• IEDM 2008 - 2nd Update
• IEDM 2008 - Update
• IEDM 2008 Preview
• VLSI 2008 Symposium Highlights
  
• VLSI 2008 Technology Program
  
• Low-k Dielectrics Status and 45 nm Process
• Interconnect Issues and 45 nm Process
• TSMC 40nm Process Expected in Second Quarter 2008
  
• Diode Lasers (LED): New Materials can extend life
  
• IEDM 2007 Highlights
  
• Intel's 45-nm High-k Metal-Gate Process
  
• Intel's 45-nm Process: High-k First, Metal-Gate-Last Integration
  
• Rapid-Thermal Process of Atomic Layer Deposition Drastically Reduced Gate Leakage for a High-k Dielectric
  

• Advanced NMOS and PMOS (CMOS) Transistor Junction Fabrication for 45nm Node - Doping, Annealing, Source and Drain Optimization, Ion Implantation, Spreading Resistance.
  
• Copper Interconnect for 45nm Process
  
• Characterization Tools Overview of Copper Metal Interconnect Integration -   Chemical, Physical, Structural, Electrical, Depth Profile, Morphology, Surface Pattern.
  
• Contact-Hole Etch Profile and CD Control Improves by Using a Polymer - Impact of thinner resist (PR) layer, Bottom Anti reflective coating (ArF, BARC), and thinner mask.
  
• CMP-Chemical Mechanical Planarization
  
• Post-Etch Residue and Photoresist Removal - removal of photoresist (PR) in the front-end-of-line (FEOL), post ion implantation, and back-end-of-line (BEOL) following etching. 
  

• Gas System - Fluorocarbon (CF4, CHF3) Used for Dielectric Material - Etch, Diffusion Issues
  
• Manufacturable Ultralow-k and Low-k Dielectrics
  
• Review of Electrical Requirements and Issues with Thermal, Mechanical, and Chemical Properties of Low-k Interlevel Dielectric
  
• Chemical Vapor Deposition (CVD) vs Atomic Layer Deposition (ALD) for High-k Dielectric
  
• Process Steps Integration Issues for Metal Gates in CMOS Technologies
  
• Process Integration Concerns of High-k/ Low-k, Cu, Metal Gate, and CVD or ALD Deposition
  
• Review of Future  High-k Gate Dielectrics Including Hafnium (Hf)-based Materials
  
• Samsung's SDRAM Process with High-k Capacitor Manufactured by ALD Process and Recessed Channe Array Transistors (RCAT) 
  
• Hitachi 90-nm Manufacturing Process - Full Single Wafer Fabrication
  

   

• The International Technology Roadmap for Semiconductors (ITRS) ITRS_Roadmap for Lithograph and CMP Planarization - Immersion and Extreme Ultraviolet (EUV) Lithography, CVD and PVD deposition and Planarization
  
• Atomic Layer Deposition (ALD) Manufacturing - Batch versus Single Wafer, Deposition Temperature, Step Coverage, Uniformity
  
• Atomic Layer Deposition (ALD) Used For Copper Seed and High-k Dielectric Processes for Logic and DRAM Products
  
• ALD Two-step Process Cycle - Chemical Gas Injection, Film Thickness, Uniformity, Composition
  
• AMD, IBM dual-stress liner (DSL) technique for straining both the NMOS and PMOS transistor channels
  
• Intel still Leads in 65-nanometer Technology Race, but  — Texas Instruments, Xilinx, and AMD Catching Up
  
• Self-Aligned SiGe BiCMOS using selective Epi (SEG)
  
• Activation of Sb during Solid-Phase Epi and Deactivation during Subsequent Thermal Process
  

• IEDM Technical Program - 2007
  
• Intel's High-k Dielectric and Metal Gate Process Solution
  
• Device Engineers are Reconsidering Germanium Transistor
  
• Lithography Trends and New Patterning Materials
  
• Physics of Strained Silicon
  
• Manufacturing Sub 50nm DRAM and NAND Flash
  
• SPIE Advanced Lithography Conference -Troubling Signs for Often-delayed EUV Technology
  
• Applied claims Two Masking Breakthroughs: Self-aligned Double Patterning Technology and a Hardmask Systemask System
  
• Hi-k Dielectric Metal Gate Integration Delays Introduction of FinFET
  
• Intel, IBM, NEC announce Hi-k Metal gate Breakthrough
  
• Process Integration Issues for 45 and 32 nm Technologies
  
• Enhancing Multi-gate Si MOSFET Performance