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VLSI 2008 Symposium Highlights
VLSI 2008 Technology Program
Low-k Dielectrics Status and 45 nm Process
Interconnect Issues and 45 nm Process
TSMC 40nm Process Expected in Second Quarter 2008
Diode Lasers (LED): New Materials can extend life
IEDM 2007 Highlights
Intel's 45-nm High-k Metal-Gate Process
Intel's 45-nm Process: High-k First, Metal-Gate-Last Integration
Rapid-Thermal Process of Atomic Layer Deposition Drastically Reduced Gate Leakage for a High-k Dielectric
Advanced NMOS and PMOS (CMOS) Transistor Junction Fabrication for 45nm Node - Doping, Annealing, Source and Drain Optimization, Ion Implantation, Spreading Resistance.
Copper Interconnect for 45nm Process
Characterization Tools Overview of Copper Metal Interconnect Integration - Chemical, Physical, Structural, Electrical, Depth Profile, Morphology, Surface Pattern.
Contact-Hole Etch Profile and CD Control Improves by Using a Polymer - Impact of thinner resist (PR) layer, Bottom Anti reflective coating (ArF, BARC), and thinner mask.
CMP-Chemical Mechanical Planarization
Post-Etch Residue and Photoresist Removal - removal of photoresist (PR) in the front-end-of-line (FEOL), post ion implantation, and back-end-of-line (BEOL) following etching.

Gas System - Fluorocarbon (CF4, CHF3) Used for Dielectric Material - Etch, Diffusion Issues
Manufacturable Ultralow-k and Low-k Dielectrics
Review of Electrical Requirements and Issues with Thermal, Mechanical, and Chemical Properties of Low-k Interlevel Dielectric
Chemical Vapor Deposition (CVD) vs Atomic Layer Deposition (ALD) for High-k Dielectric
Process Steps Integration Issues for Metal Gates in CMOS Technologies
Process Integration Concerns of High-k/ Low-k, Cu, Metal Gate, and CVD or ALD Deposition
Review of Future High-k Gate Dielectrics Including Hafnium (Hf)-based Materials
Samsung's SDRAM Process with High-k Capacitor Manufactured by ALD Process and Recessed Channe Array Transistors (RCAT)
Hitachi 90-nm Manufacturing Process - Full Single Wafer Fabrication
The International Technology Roadmap for Semiconductors (ITRS) ITRS_Roadmap for Lithograph and CMP Planarization - Immersion and Extreme Ultraviolet (EUV) Lithography, CVD and PVD deposition and Planarization
Atomic Layer Deposition (ALD) Manufacturing - Batch versus Single Wafer, Deposition Temperature, Step Coverage, Uniformity